The following co-pending U.S. patent application is believed to be relevant: Ser. No. 08/847,239 filed Apr. 30, 1997 to Saran et al, now U.S. Pat. No. 6,143,396.
1. Field of the Invention
The invention is generally related to the field of integrated circuits and more specifically to improving the mechanical stability of interconnects under bond pads in an integrated circuit.
2. Background of the Invention
A well known problem area in semiconductor processing is the process of attaching a solder, wire or other bonding elements to a bond pad on a semiconductor integrated circuit. These bond pads are typically disposed above one or more layers or stacks of brittle and/or soft dielectric materials, typically oxides of silicon and some organic materials, for planarization and insulation purposes. Some dielectric materials, such as hydrogen silsesquioxane (HSQ), organo-silicate glass (OSG), aerogels, organic polyimides, parylenes, and others are advantageous for their low dielectric constants compared to silicon oxides, but are weaker structurally and mechanically.
During the bonding process, mechanical loading and ultrasonic stresses applied by the bonding capillary tip to the bond pad often result in fracture of the underlying dielectrics, deformation of the underlying metal structures, and delamination of the layers in the metal structures. These bonding failures may appear as craters in the bond pad and underlying layers as the bonding capillary tip is pulled away from the bonding pad. However, these defects often are not apparent during bonding but would manifest themselves during subsequent bond pull and shear tests, reliability tests such as thermal cycle or thermal shock, or upon deprocessing and cross-sectioning.
Further, weakness of the bond pad structure may also reveal itself during wafer probing prior to bonding. Again, the stresses exerted by the probe tips, typically formed of a hard metal such as tungsten and copper beryllium, can cause localized fractures in the pads, despite the fact that they make contact with softer metals such as aluminum and copper, on the bond pads. Such fractures are as much of a reliability hazard as those caused during bonding.
Traditionally, the bonding failures have been addressed by altering bonding parameters, such as ultrasonic power and pulse waveform, bonding temperature, bonding time, clamping force, shape of the bonding capillary tip, etc. Much time is spent experimenting with parameter settings and combinations thereof. Although general guidelines of parameter setpoints and configurations have been developed, the bonding failures persist at a sufficiently significant level to continually threaten the reliability of integrated circuit devices. Yet the failure levels are low such that bonding failures become apparent only after several tens of thousands of devices are bonded.
Recent technological advances in semiconductor processing do not alleviate the situation. New dielectric materials with lower dielectric constants are being used to increase circuit speeds but they are mechanically weaker than the conventional plasma enhanced chemical vapor deposition (CVD) dielectrics. Decreasing bond pad dimensions necessitates the increase of stresses due to the bonding process attributable to the use of ultrasonic energy to form effective bonds. Inaccessibility of higher bond parameter settings for fear of damage to the bond pads also results in longer bond formation time, and consequently, lost throughput. All these significant changes point to a trend of more severe failures and increase in their frequency.
The invention uses a conductive via pattern or group between the bond pad of the uppermost metal interconnect layer (Mn) and a metal pad on the next underlying metal interconnect layer (Mnxe2x88x921). The conductive via pattern strengthens the interlevel dielectric (ILD) between Mn and Mnxe2x88x921. By spreading the stress concentration laterally, the conductive via pattern inhibits microcracking in the ILD from stress applied to the bond pad.
An advantage of the invention is providing an integrated circuit having reinforced interconnects to prevent microcracking during probing, wire bonding, or packaging.
This and other advantages will be apparent to those of ordinary skill in the art having reference to the specification in conjunction with the drawings.